Nonvolatile memory devices retain data even in the absence of a power supply. Flash memories, which are a type of nonvolatile memory device, are widely used in computers and memory cards because they have many preferred characteristics, including the ability to be erased efficiently. Flash memories are often distinguished into NAND and NOR types, based on how the memory cells are connected to bitlines. A NOR flash memory is configured so that a bitline is connected to two more cell transistors in parallel, storing data by way of channel hot-electron effect and erasing data by way of the Fowler-Nordheim (F-N) tunneling effect. A NAND flash memory is configured so that a bitline is connected to two more cell transistors in series, storing and erasing data by way of the F-N tunneling effect. NOR flash memories may be disadvantageous for high integration density because they dissipate much current, but are advantageous for adapting high-frequency operations. NAND flash memories may be advantageous when seeking high integration density because they consume significantly less current than NOR flash memories.
FIG. 1 is a circuit diagram showing a memory cell array 10 of a general NAND flash memory device. The flash memory device, also known as a flash EEPROM (electrically erasable and programmable read-only-memory), includes the memory cell array 10 that is composed of plurality of floating-gate cell transistors. The memory cell array 10 is constructed with multiple memory blocks in which pluralities of bitlines BL1˜BLm are arranged in parallel. Each memory block includes pluralities of cell strings (or “NAND strings”) which correspond each to the bitlines BL1˜BLm. The circuit configuration of a plurality of cell strings belonging to a single block is shown in FIG. 1.
As shown in FIG. 1, each NAND string includes a string selection transistor SST, a ground selection transistor GST, and multiple floating-gate cell transistors M0˜M31 (e.g., 32 in number) that are serially connected between the source of the string selection transistor SST and the drain of the ground selection transistor GST. The drain of the string selection transistor SST included in each string is connected to the bitline corresponding thereto, and the source of the ground selection transistor GST is connected to a common source line (or common signal line) CSL. The gates of the string selection transistors SST of the NAND strings are coupled to a string selection line SSL in common, and the gates of the ground selection transistors GST are connected to a ground selection line GSL. The control gates of the floating-gate cell transistors M0˜M31 included in each NAND string are coupled respectively to wordlines WL0˜WL31. The bitlines BL1˜BLm are electrically connected to a page buffer circuit (not shown) of the flash memory device.
The ground selection line GSL, the wordlines WL0˜WL31, and the string selection line SSL are connected each to signal selection lines, GS, Si0˜Si31, and SS, through block selection transistors BS0˜BS33, respectively. The block selection transistors BS0˜BS33, which are included in a row decoder circuit (not shown) of the flash memory device, are controlled by a block-selection control signal BS. The signal selection lines, GS, Si0˜Si31, and SS, are driven by selection circuits (or drive circuits) during each programming operation. The block-selection control signal BS is configured to have a high voltage level, when active, so as to make a program or pass voltage sufficiently transferred to the wordlines WL0˜WL31 via the signal selection lines Si0˜Si31.
The floating-gate cell transistors, within memory cells M0˜M31, are first erased to have a predetermined threshold voltage (e.g., −3V). Then, during programming, a high voltage (e.g., 20V) is applied to a wordline of a selected memory cell to thereby conduct a practical programming operation for the selected memory cell. In order to accomplish a successful programming result for the selected memory cell, a threshold voltage of the selected memory cell must be increased while the rest of the deselected memory cells are maintained without change. However, as shown in FIG. 1, since the control gates of the floating-gate cell transistors M0˜M31 included in the cell strings are connected to the wordlines WL0˜WL31 in common along rows, some problems may occur during the programming operation as follows. When a program voltage is supplied to a selected wordline, the program voltage is applied also to deselected memory cells arranged along the same wordline as well as the selected memory cell. As a result, the deselected memory cell, which is arranged along the same wordline, may become programmed. Thus, accidental programming may result for a deselected memory cell connected to a selected wordline. This accidental programming is caused by a phenomenon known as “program disturbance.”
Several ways of preventing the effect of program disturbance have been proposed. For example, program inhibition by a self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873, entitled METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN, and in U.S. Pat. No. 5,991,202 entitled METHOD OF REDUCING PROGRAM DISTURB DURING SELF-BOOSTING INA NAND FLASH MEMORY. Program inhibition by a local self-boosting scheme is disclosed in U.S. Pat. No. 5,715,194, entitled BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY, and in U.S. Pat. No. 6,061,270, entitled METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL. The program-inhibiting method by the local self-boosting scheme raises a channel boosting voltage of a program-inhibited cell transistor higher than the method by the self-boosting scheme. Thus, the local self-boosting scheme is widely used in programming multi-level memory cells in a flash memory device.
However, even with the aforementioned program-inhibiting methods, the problem of program disturbance may still be present as the integration density of the flash memory device gradually increases. This is because an increase in the integration density of the flash memory device narrows intervals between adjacent memory cells and between adjacent signal lines and this narrowing increases the probability of coupling interference. In particular, since the program voltage applied to a selected wordline is set at a very high level relative to a power source voltage of the flash memory device, the probability of a high voltage influencing the voltages on wordlines adjacent to a selected wordline increases.
FIG. 2 is a schematic diagram illustrating a soft-programming effect that is generated in a program-inhibited memory cell as the flash memory device is increased in integration density. In FIG. 2, there is shown the configuration of potentials formed in channels of the program-inhibited cell 120 and memory cells 110 and 130 adjacent thereto while employing a programming method that includes a local self-boosting scheme.
Referring to FIGS. 1 and 2, in the programming method with the local self-boosting scheme, a bitline voltage of 0V is first applied to a selected bitline (i.e., a bitline connected to floating-gate cell transistors to be programmed), while a power source voltage Vcc is applied to a deselected bitline (i.e., a bitline connected to floating-gate cell transistors to be program-inhibited).
And then, a decoupling voltage of 0V is applied to two deselected wordlines, WLn−1, and WLn+1, immediately adjacent to a selected wordline WLn, while a pass voltage Vpass of 10V is applied to other deselected wordlines. During this step, a drain voltage of the floating-gate cell transistor 130, which is coupled to the upper wordline WLn+1, and a source voltage of the floating-gate cell transistor 110, which is coupled to the lower wordline WLn−1, is raised through a boosting operation by the pass voltage Vpass. As a result, the memory cells, 110 and 130, to which the decoupling voltage is applied, are shut off to thereby electrically isolate channels of the rest of the cells from the channel of the memory cell 120, to which the program voltage Vpgm is applied. This cuts off the current flowing into the memory cells 110 and 130 that are located adjacent to the source and drain of the program-inhibited cell 120.
In this case, the potentials formed in the channels of the memory cells, 110 and 130, which are immediately adjacent to the source and drain of the program-inhibited cell 120, are noticed by P1 and P4 shown in FIG. 2, respectively. As illustrated in FIG. 2, the potential P1, which is formed in the channel of the lower memory cell 110 of the program-inhibited cell 120, is larger than the potential P4, which is formed in the channel of the higher memory cell 130 of the program-inhibited cell 120. This is because the threshold voltage of the lower memory cell 110 has been already raised up to 1V before the program voltage Vpgm is applied to the selected wordline WLn. As well known, the programming operation begins first to the memory cell nearest to the ground selection line GSL, proceeding toward the string selection line SSL in sequence. Accordingly, while the memory cell 130 coupled to the upper wordline WLn+1 of the wordline WLn is held on an erased state with the threshold voltage of −3V (i.e., a low potential state) when a memory cell coupled to the wordline WLn is being programmed, the memory cell 110 coupled to the lower wordline WLn−1 of the wordline WLn may be conditioned in a programmed state with the threshold voltage of 1V (i.e., a high potential state).
Continuously, when the program voltage Vpgm is applied to the selected wordline WLn, a channel voltage of the program-inhibited cell 120 is boosted up to the level of the program voltage Vpgm. The boosted channel voltage Vbst of the program-inhibited cell 120 is summarized as follows.Vbst=(Vcc−Vth—SSL)/n+Vpgm*Cin/(Cin+Cch)   [Equation 1]
Here, the parameter Vth_SSL represents a threshold voltage Vth of the string selection transistor and the parameter Cch represents channel capacitance. The parameter Cin is defined as Cin=Cono*Ctunn/(Cono+Ctunn) and the parameter n means the number of the floating-gate cell transistors belonging to a string (e.g., 32). The parameter Cono denotes capacitance of an oxide-nitride-oxide (ONO) film interposed between floating and control gates in the program-inhibited cell 120, and the parameter Ctunn denotes capacitance of a tunnel oxide film interposed between the floating gate and the semiconductor substrate in the program-inhibited cell 120.
According to an increase of the channel voltage of the program-inhibited cell 120 to which the program voltage Vpgm is applied, as shown by the Equation 1, it decreases the potential between the floating gate and channel in the program-inhibited cell 120 (refer to P3 of FIG. 2). As a result, there is no generation of the F-N tunneling effect between the floating gate and channel in the program-inhibited cell 120, preventing the memory cell 120 from being programmed.
Meanwhile, as the program voltage Vpgm is very high as much as reaching 20V, it boosts up channel voltages of the memory cells 110 and 130 those are adjacent to the program-inhibited cell 120, as well as the program-inhibited cell 120. Here, a voltage range ΔVB1 available to be increased in the channel of a memory cell adjacent to the program-inhibited cell 120 (i.e., the memory cell 110 located at the lower side of the program-inhibited cell 120), is relatively lower than a voltage range ΔVB3 available to be increased in the channel of the program-inhibited cell 120. Thus, there is generated a potential difference ΔP, higher than a level, in an N-well region (i.e., a common source-drain region of the memory cells 110 and 120 adjacent to each other) through which the program-inhibited cell 120 links with the memory cell 110 located lower than the cell 120. Thereby, electrons are accelerated to move toward the floating gate of the program-inhibited cell 120 (see the arrow {circle around (1)} in FIG. 2). On the other hand, as the program voltage Vpgm is charged on the floating gate of the program-inhibited cell 120, there is generated a vertical electric field between the floating gate and channel of the program-inhibited cell 120 (see the arrow {circle around (2)}). Due to this electric field, a problem occurs because the accelerated electrons (i.e., hot carriers) are injected into the floating gate of the program-inhibited cell 120. As such, an effect of increasing the threshold voltage of the program-inhibited cell 120 by hot carriers is called “soft-programming”, which increases the threshold voltage of the program-inhibited cell 120 and thereby causes the program-inhibited cell 120 to be inadvertently programmed. Therefore, as the integration density of the flash memory device is increased, it is necessary to prevent the problem of program disturbance such as the soft-programming effect.